1. Technical Field of the Invention
The present invention relates to acknowledging commands in a system/power management bus environment and, more specifically, to the acknowledgement of unsupported command codes by a slave device.
2. Description of Related Art
The System Management Bus (SMBus) is a bus defined by Intel in 1995. The SMBus is primarily used in personal computers and servers for low-speed system management communications. See, “System Management Bus (SMBus) Specification”, Version 2.0, dated Aug. 3, 2000, the disclosure of which is hereby incorporated by reference.
The Power Management Bus (PMBus) is a bus defined in accordance with an open standard power-management protocol. The protocol supports a fully defined command language that facilitates communication with power converters and other devices in a power system. See, “PMBus Power System Management Protocol Specification Part I—General Requirements, Transport and Electrical Interface” Revision 1.1, Feb. 5, 2007, the disclosure of which is hereby incorporated by reference. See, also, “PMBus Power System Management Protocol Specification Part II—Command Language” Revision 1.1, Feb. 5, 2007, the disclosure of which is hereby incorporated by reference.
Reference is now made to FIG. 1 which shows a block diagram of the interconnection of a system host/bus master 10 with a slave unit 12 through a Power Management Bus (PMBus). The slave unit 12 will typically comprise a power conversion device or a power system device. The system host/bus master 10 includes an input 14 connected to an alert signal line 16. The slave unit 12 includes an output 18 which is connected to the alert signal line 16. The slave unit 12 can use the alert signal line to issue an alert signal (for example, through a logic state change) indicating the signaling of an alert condition. The system host/bus master 10 includes an output 20 connected to a control signal line 22. The slave unit 12 includes an input 24 which is connected to the control signal line 22. The control signal line 22 carries a control signal output from the system host/bus master 10 so as to turn the slave unit 12 on and off in conjunction with the issuance of commands by the system host/bus master 10). The system host/bus master 10 further includes an output 26 connected to a clock signal line 28. The slave unit 12 includes an input 30 which is connected to the clock signal line 28. The clock signal line 28 carries the clock signal generated by the system host/bus master 10 which governs timing of operations on the PMBus. The system host/bus master 10 also includes a serial input/output 30 connected to a bi-directional serial data bus 32. The slave unit 12 includes a serial input/output 34 which is connected to the bi-directional serial data bus 32. The serial data bus 32 carries bus communications (such as commands and data issued by the system host/bus master 10 or data originating at the slave unit 12) between the system host/bus master 10 and the slave unit 12. The slave unit 12 further receives address programming data (specifying the particular address of the slave unit) and a write protect signal (which is optional for controlling the updating of internal memory within the slave unit 12). Although only one slave unit 12 is shown in FIG. 1, it will be understood by those skilled in the art that the PMBus supports the connection of multiple slave units to the system host/bus master 10, and furthermore more than one bus master 10 may be connected.
Reference is now made to FIG. 2 which shows an exemplary communication between the system host/bus master 10 and the slave unit 12 over the serial data bus 32. In FIG. 2, an open box 50 indicates a master-to-slave serial communication over the bi-directional serial data bus 32 while a shaded box 52 indicates a slave-to-master communication over the bi-directional serial data bus 32. The illustrated serial communication in FIG. 2 is read from left to right. Thus, the master 10 sends a first bit S indicating a “start condition” over the serial data bus 32. The master 10 than sends a seven bit address of the slave 12 to which the master's communication is addressed followed by a one bit Wr indicating a “write” operation (or Wr(bar) indicating a “read” operation) to be performed with respect to the slave 12. The addressed slave 12 responds to the communicated eight bits (address plus Wr) with a one bit A signal indicating an acknowledgement (ACK) of receipt. The master 10 then sends an eight bit command code to the slave 12 instructing the performance of a certain operation by the slave 12. The previously addressed slave responds to the communicated eight bits of command data with a one bit A signal indicating an acknowledgement (ACK) of receipt. The master 10 may then send, for example, an eight bit data byte. The previously addressed slave responds to the communicated eight bits of data with a one bit A signal indicating an acknowledgement (ACK) of receipt. The master 10 then sends a one bit P signal indicating a stop condition. It will be noted that the master-to-slave communication begins with a start S bit and ends with a stop P bit. Additionally, for every successfully received byte (eight bits) the slave 12 responds with a one bit A acknowledgement. Although not shown in FIG. 2, should the slave 12 send eight bits of data to the master 10 (which are successfully received), the master 10 will likewise respond with a one bit A acknowledgement.
One question concerns what should be done by the slave 12 when the eight bit command code sent by the master 10 is not supported by the slave 12? In accordance with the SMBus standard, the slave 12 should send a one bit A(bar) signal indicating no acknowledgement (NACK) of receipt (see, “System Management Bus (SMBus) Specification”, Version 2.0, Section 5.5). In accordance with the PMBus standard, the slave 12 may either a) send a one bit A(bar) signal indicating no acknowledgement (NACK) of receipt (see, “PMBus Power System Management Protocol Specification Part II—Command Language” Revision 1.1, Section 10.9.2), or b) send a one bit A signal indicating an acknowledgement (ACK) of receipt followed by a notification to the master 10 through an Alert Signal indicating that the command which was previously sent is not supported by the slave 12 (see, “PMBus Power System Management Protocol Specification Part II—Command Language” Revision 1.1, Sections 10.2.2 and 10.6).
It is known in the art to provide a bus communication between master and slave which is not fully hardware compatible with the SMBus/PMBus specification. For example, it is possible to have a master and slave interconnected by an I2C bus. FIG. 3 illustrates a conventional I2C bus configuration with respect to a master device 10 and several slave devices 12. The conventional I2C bus configuration uses two open-drain lines, the Serial Data (SDA) line and the Serial Clock (SCL) line, pulled up with resistors to a supply voltage Vdd.
In the I2C bus configuration, the master 10 is a node that issues the clock and addresses the slaves. Each slave 12 is a node that receives the clock and the address from the master 10. The master 10 is initially in master transmit mode by sending a start bit followed by the seven-bit address of the slave 12 to which it wishes to communicate. This is followed by a single bit representing whether the master 10 wishes to write to or read from the slave. If the addressed slave 12 exists on the bus, the slave responds with a one bit acknowledgement (active low for acknowledged). The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). This I2C bus protocol is very similar to that shown in FIG. 2 for SMBus/PMBus operation.
Referring again to the issue of what should be done by the slave 12 when the eight bit command code sent by the master 10 is not supported by the slave 12, those skilled in the art will recognize that the current I2C bus protocol does not permit sending a one bit A(bar) signal indicating no acknowledgement (NACK) of receipt when the command is not supported. Thus, in an I2C bus configuration, in support of the SMBus/PMBus specification, the slave must choose option b) and send a one bit A signal indicating an acknowledgement (ACK) of receipt followed by a notification to the master 10 indicating that the command which was previously sent is not supported by the slave 12. To accomplish this, the I2C bus configuration must further include an alert signal line (ALERT), similar to the alert signal line 16 of FIG. 1, to allow the slave 12 to issue the notification to the master 10. However, the SMBus/PMBus specification specifically teaches that the alert signal line 16 of FIG. 1 is optional, and thus those skilled in the art will often not include the ALERT line in an I2C bus configuration like that of FIG. 3.
A need accordingly exists for a way to have a slave 12 issue a notification to the master 10 in a conventional I2C bus configuration that the received command which was previously sent by the master 10 is not supported by the slave 12. More specifically, there is a need to support the slave-to-master notification of no support for the issued command without requiring the presence of the optional ALERT signal line in the I2C bus configuration.